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We characterized resistance drift in phase change memory devices in the 80 K to 300 K temperature range by performing measurements on 20 nm thick, ∼70–100 nm wide lateral Ge₂Sb₂Te₅(GST) line cells. The cells were amorphized using 1.5–2.5 V pulses with ∼50–100 ns duration leading to ∼0.4–1.1 mA peak reset currents resulting in amorphized lengths between ∼50 and 700 nm. Resistance drift coefficients in the amorphized cells are calculated using constant voltage measurements starting as fast as within a second after amorphization and for 1 h duration. Drift coefficients range between ∼0.02 and 0.1 with significant device-to-device variability and variations during the measurement period. At lower temperatures (higher resistance states) some devices show a complex dynamic behavior, with the resistance repeatedly increasing and decreasing significantly over periods in the order of seconds. These results point to charge trapping and de-trapping events as the cause of resistance drift. 

Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing ( Vside ). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage ( Vt ) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm × 78 nm (width × length) device shows SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and Vt increasing from 0.42 to 0.61 V as the temperature is reduced from 400 to 100 K. Vt can be adjusted from ∼ 0.3 to ∼ 1.1 V with ∼ 0.3 V/V sensitivity by depletion or accumulation of the body of the device using Vside . This high level of tunability allows electronic control of Vt and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents ( < 10 −13 A).